The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to self-aligned patterned etch stop layers for semiconductor devices.
Metallization patterns on integrated circuits may be formed by depositing a dielectric layer, patterning the dielectric layer by photolithography and reactive ion etching (RIE) to form a groove or trench, and depositing a metal layer that fills the trench in the dielectric layer. The metal layer typically not only fills the trenches but also covers the entire semiconductor wafer. Thereafter, the excess metal is removed using either chemical-mechanical polishing (CMP) or an etch back process so that only the metal in the trenches remains. This technique, also referred to as “damascene” processing in the art, thus forms inlaid conductors in the dielectric layer. Damascene processing (an additive process) avoids the problems associated with metal etching (a subtractive process), such as, for example, the lack of suitable dry-etch plasma chemistries, problems in dimension control, the formation of small gaps that are difficult to fill with the subsequent dielectric layer, and the entrapment of impurities in inter wiring spaces.
In a dual damascene process, a monolithic via/line structure is formed from the repeated patterning of a single thick dielectric layer, followed by metal filling and CMP. First, a relatively thick dielectric layer (e.g., oxide, low-K material) is deposited on a planar surface. The dielectric thickness may be slightly larger than the desired final thickness of the via and line, since a small amount of dielectric material is removed during CMP. Via recesses are formed in the dielectric layer using photolithography and RIE that either partially etches through the dielectric or traverses the dielectric and stops on the underlying metal to be contacted. The line recesses (trenches) can then be formed using a separate photolithography step and a timed etching step. In lieu of forming the via recesses first, the trenches may be formed first followed by via recess formation.
In either instance, the via/line metallization is then deposited, and thereafter planarized using CMP. The resulting interconnects are produced with fewer process steps than with conventional single damascene processing. Moreover, with a dual damascene process, two layers of metal are formed simultaneously (e.g., a wiring line and contact stud vias), thus avoiding an interface therebetween.
On the other hand, existing dual damascene integration schemes with a homogeneous dielectric material (i.e., without buried etch stop layers therein) generally suffer from through-pitch dependent RIE lag, and pattern density dependent trench depth control. One common method to reduce these effects is to utilize buried etch stops within the dielectric layer. However, such a solution involves materials that typically hurt the overall effective dielectric constant of the material due to the nature of the materials that are required for the process. Alternatively, the benefits of dual damascene processing may be surrendered by reverting to single damascene processing.